1. Field of the Invention
The present invention relates to a signal generator, and more particular to a signal generator that generates a plurality of output signals using a counted value of a counter as a trigger.
2. Description of Related Art
There are generally known a solid state imaging apparatus such as a video camera and a digital still camera that use a solid state imaging device such as a charge coupled device (CCD). Such a solid state imaging apparatus includes a control circuit controlling respective functions of an imaging unit, a signal processing unit, a record processing unit and the like, and is further equipped with a signal generator, a so-called timing generator (TG), which generates a signal to regulate the operation timing of each unit.
Now, it is necessary to drive a vertical CCD and a horizontal CCD at a suitable timing in order to read signal charges from two-dimensionally arranged photodiodes and to transfer the read signal charges using the CCD's. The suitable timing for transferring the signal charges is different depending on respective operation modes, such as a normal photographing mode, in which the resolution of a screen is high, and an autofocus mode, in which a processing speed is regarded as important. In other words, the output signals, i.e., drive timing pulses, that are required for a TG are different according to the respective operation modes. As a result, the drive timing pulses required for the TG sometimes vary in several tens of kinds.
As described above, the TG is required to generate suitable drive timing pulses in accordance with the respective operation modes. In a case of trying to configure such a TG with only logic circuits, the logic circuits to be configured are determined in respect of hardware (circuits, devices, wiring and the like) on the basis of the drive timing pulses to be generated. Consequently, when the drive timing pulses required for the TG are altered, it is obliged to perform another trial manufacture of the logic circuits.
It is noted that the requirements of the miniaturization and the increase of the number of pixels of a CCD have been increasing year by year in the markets of digital still cameras and camcorders, and the drive timing pulses required for the TG have been also diversified.
Moreover, although it is also considerable to start the development of a TG after the determination of the drive timing pulses required for the TG in order to avoid performing such trial manufactures of the logic circuits, it may be difficult to prepare the TG for driving a CCD made on an experimental basis at the time of the shipment of the CCD by such a method.
Moreover, when the structure and the number of pixels of a CCD have been changed, the drive timing pulses required for a TG are also changed generally, and consequently it is not preferable to deal with the changes of the CCD by developing and commercializing a TG on all such occasions because the aforesaid delay of the time of the shipment of the TG to the CCD may be caused and further, the commoditization of a set substrate may be hindered.
Accordingly, there has been proposed a technique of not configuring a TG only with the logic circuits, but storing the data necessary for generating the drive timing pulses required for the TG into a memory built in the TG, for example, in Japanese Patent Application Publication (KOKAI) No. Hei 1-181384 (patent document 1).
Now, by building the memory into the TG to store necessary data into the memory, even if an alteration of the drive timing pulses required for a TG occurs after the TG has been made on an experimental basis, the alteration can be dealt with by altering the data to be stored in a memory. Consequently, the problems mentioned above can be solved. But, because the number of the drive timing pulses to be used for the drive of a solid state imaging device is generally large and the waveforms of the drive timing pulses are complicated, the amount of data to be stored in the memory becomes large.
For dealing with the problem, there has been proposed a technique for achieving the reduction of the amount of data to be stored in a TG, for example, in Japanese Patent Application Publication (KOKAI) No. 2002-51270 (patent document 2). By the technique, as for the drive timing pulses that change with several kinds of correlations, the data indicating a repetition pattern of a certain pulse is stored in a time series data memory. A control value indicating the length of a period from a changing point of a certain drive timing pulse to the next changing point of a drive timing pulse, i.e., logical change unit, is stored in a first memory. The number of the logical changes of pulses during one cycle is stored in a second memory. A desired number of repetition cycles are stored in a third memory. Desired drive timing pulses are obtained by a multiple counting operation using the data in these memories.
However, for example, the drive timing pulses in which the length of a period of a changing point of a certain drive timing pulse to the next changing point of a drive timing pulse is not fixed are shown in FIG. 7. In concrete terms, the drive timing pulses are different from one another in a period denoted by a mark a in FIG. 7, a period denoted by a mark b in FIG. 7 and a period denoted by a mark c in FIG. 7. In this case, the drive timing pulses cannot be divided into logical change units. Consequently, the technique disclosed in the patent document 2 cannot be applied to such drive timing pluses.
In addition, although it is possible to apply the technique of the patent document 2 by dividing the logical change units, in concrete terms, the period denoted by the mark a in FIG. 7, the period denoted by the mark b in FIG. 7, the period denoted by the mark c in FIG. 7 and the like, in pieces to be one unit and by using such a fine unit as a reference, the amount of the data to be stored in a memory becomes very large in such a case.
Accordingly, a TG configured as follows is generally used. That is, as shown in FIG. 8, the TG is provided with n bit registers the number of which is equal to the number of the outputs of drive timing pulses and n bit comparison circuits CMP corresponding to the respective registers. The n bit resisters include n bit set registers SET and n bit reset registers RST. The data of a rising timing of each drive timing pulse of the mode to be an object among the data of a plurality of modes stored in a main memory (e.g. a random access memory (RAM)) 101 is written in a set register through a buffer 102 based on an instruction from a control circuit 100, and the data of the falling timing of each drive timing pulse is written in a reset register through the buffer 102. The rising timing is the timing when the level of the drive timing pulse changes from a low level (L level) to a high level (H level), and the falling timing is the timing when the timing pulse changes from the H level to the L level. Each of the comparison circuit CMP compares the timing written in the register with a counted value of an n bit counter 103. If the counted value of the counter 103 reaches the timing written in the set register, that is, the counted value written in the set register, the TG makes the drive timing pulse rise. If the counted value of the counter 103 reaches the timing written in the reset register, i.e., the counted value written in the reset register, the TG makes the drive timing pulse fall.
It is noted that a microcomputer in FIG. 8 outputs mode data corresponding to an operation and control of an external set, such as camera main body or the like, to a microcomputer interface, and the microcomputer interface outputs the mode data of the TG corresponding to the mode data of the microcomputer to the control circuit 100. Moreover, a synchronization signal in FIG. 8 is directly output from the microcomputer to the control circuit 100 in order to synchronize the other devices in the external set with the TG.
Furthermore concretely speaking, the TG writes the timing, i.e., the counted value of the counter 103, when a drive timing pulse Vt (t=1, 2, . . . x) rises into a set register SETt, and writes the timing, i.e., the counted value of the counter 103, when the drive timing pulse Vt falls into a reset register RSTt. Then, the TG compares the counted values written in the set register SETt and the reset register RSTt with the counted value of the counter 103 with the comparison circuits CMP. The TG makes a timing pulse Vt rise at the timing when the counted value of the counter 103 reaches the counted value written in the set register SETt, and makes the timing pulse Vt fall at the timing when the counted value of the counter 103 reaches the counted value written in the reset register RSTt.
Now, it is for making the TG have versatility to write the data indicating the position of a rise or a fall of the drive timing pulse into the n bit register, and a description is given to the respect. In addition, the following description is given on the supposition that the writing of the data into the register is performed in the form of the data of a binary number.
For example, a mode in which the drive timing pulse Vt is made to rise when the counted value of the counter 103 is 10 and the drive timing pulse Vt is made to fall when the counted value of the counter 103 is 50 is referred to as an A mode, and a mode in which the drive timing pulse Vt is made to rise when the counted value of the counter 103 is 100 and the drive timing pulse Vt is made to fall when the counted value of the counter 103 is 500 is referred to as a B mode. In this case, it is possible to deal with the A mode by providing a register of 6 bits because the register can deal with the counted value of the counter 103 up to 64 (=26). But, a register of 9 bits that can deal with the counted value of the counter 103 up to 512 (=29) becomes necessary if it is wanted to deal with the B mode. This fact means that, in a case where the data indicating a rise position or a fall position of a drive timing pulse is written in the register of 9 bits, it is possible to deal with both of the A mode and the B mode.
As described above, in order to make it possible to deal with various modes, and in order to make a TG have versatility, it is preferable that the register in which the data indicating a rise position or a fall position of a drive timing pulse is written has the number of bits (n bit) with an adequate spare in consideration of the number of modes expected in future, for example.
Then, if data (a counted value) is written into the register of n bits, the comparison circuit CMP that compares the counted value written in the register with the counted value of the counter 103 is also required to have n bits.